1. Technical Field
The present invention relates to data processing systems, and more particularly to apparatus for programming the signal lines between a memory control unit and a memory array.
2. Background Art
Present day dynamic random access memories (eg. DRAMs) are controlled by memory control units (MCUs). These MCUs match the speed of different arrays by providing different fixed speeds at which the arrays can be operated, with the appropriate array control signal timings specified for each speed. Existing memory control units provide only two or three fixed timings of differing durations, and lack the flexibility of being able to accommodate DRAM control signal timings that vary from manufacturer to manufacturer.
Furthermore, providing two or three fixed timings of differing durations results in poor memory performance in many cases because the fineness of the signal timing adjustment is too coarse. It is desirable to be able to fine tune signal transitions to a fraction of a memory cycle.
It is also desirable to have a memory control unit that will generate any pattern of control signal timings to provide a range of timing controls for DRAM operations.
Because the pattern of control signal timings is used for DRAM control, there are some special requirements which are needed to meet high-performance timings. Instead of dealing with these as many special cases, it is desirable to integrate them as much as possible into the memory control unit. This reduces random logic and reduces design complexity.
It is an object of this invention to provide a memory array timing that is programmable, flexible, allows fine tuning to a fraction of a memory cycle, and is not overly complex.